Three dimensional hexagonal matrix memory array

ABSTRACT

A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

The present application is a continuation of U.S. Application serialnumber 12/005,346, filed Dec. 27, 2007, now U.S. Pat. No. 7,746,680 theentire contents of which is incorporated herein by reference.

BACKGROUND

The present invention relates generally to the field of semiconductorsand more specifically to the field of memory devices.

As half-pitches approach process nodes that are unsustainable byconventional lithography systems, techniques such as double exposure ordouble patterning have been used to extend the capabilities ofconventional lithography equipment to shorter half-pitches. Doubleexposure, as its name implies, consists of exposing a single coating ofresist twice, using two different masks. Features that are closetogether are exposed separately in order to counter the undesirableoverexposure which is a consequence of non-contact lithography methods.

Conventional memory array layout is rectangular. The memory cells of amemory array are laid out as a rectangular (Cartesian) grid. Thestandard rectangular layout is used because it is the logical way tostructure an array and because conventional semiconductor processes aredesigned for a rectangular layout.

However, the half-pitch of a rectangular layout cannot be effectivelyreduced with double exposure techniques. For example, if the bit andword lines can be reduced by a factor of 2 using double exposure, thespacing of the layout of the memory cells can only be reduced by afactor of 1.4 using double exposure.

SUMMARY

One embodiment of the invention relates to a nonvolatile memory device.The nonvolatile memory device includes a plurality of nonvolatile memorycells arranged in a substantially hexagonal pattern.

Another embodiment of the invention relates to a nonvolatile memorydevice, comprising a plurality of word lines, a plurality of bit lines,and a nonvolatile memory cell array comprising a plurality ofnonvolatile memory cells. The plurality of word lines cross theplurality of bit lines at an angle of about 60 degrees in the memorycell array. The plurality of nonvolatile memory cells in the nonvolatilememory cell array are arranged in a plurality of subarrays which aresubstantially parallelogram shaped.

Another embodiment of the invention relates to a method of making adevice using a self-assembling material. A self-assembling materiallayer is formed over at least one device layer. The self-assemblingmaterial forms a plurality of openings that expose a first surface ofthe at least one device layer. A hard mask material layer is formed overthe self-assembling material layer such that the hard mask materialfills the plurality of openings in the self assembled material. The hardmask material is removed such that the hard mask material patternsremain in the plurality of openings and an upper surface of theself-assembling material layer is exposed. The remaining self-assemblingmaterial layer is removed. The at least one device layer is etched usingthe patterned hard mask patterns as a mask to form a plurality of pillarshaped devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a memory cell subarray in accordance with anexemplary embodiment.

FIG. 2 is a diagram of a hexagonal pattern.

FIG. 3 is a top view of the bit line and word line layout of the memorycell subarray of FIG. 1 in accordance with an exemplary embodiment.

FIGS. 4A, 4B, 4C and 4D are top views of an array of memory subarrays inaccordance with an exemplary embodiment.

FIG. 5 is a perspective view of a memory subarray in accordance with anexemplary embodiment.

FIG. 6 is a diagram showing a triple exposure process of a memory cellarray in accordance with an exemplary embodiment.

FIG. 7 is a diagram showing a double exposure process of bit lines andword lines in accordance with an exemplary embodiment.

FIG. 8 is a diagram showing a quadruple exposure process of a memorycell array in accordance with an exemplary embodiment.

FIG. 9 is a diagram showing a self-assembly polymer process of a memorycell array in accordance with an exemplary embodiment.

FIG. 10 is a flowchart showing a self-assembly polymer process of amemory cell array in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

Hexagonal Memory Subarray Structure

Referring to FIG. 1, a top view of a memory cell subarray 100 inaccordance with a first embodiment is shown. The memory cell subarray100 is part of a larger memory array (not depicted) which can be formedon a single die. A subarray boundary 105 of the memory cell subarray 100is substantially parallelogram shaped. In other words, the subarray 100has a four sided shape with at least two parallel sides (and preferablywith two sets of parallel sides) having a one non-square corner. Theterm “substantially” parallelogram shaped includes small deviations fromthe parallelogram shape, such as non-straight boundary lines and/orsmall protrusions or recesses in the boundary. Preferably, the anglebetween two adjacent sides at the non-square corner is 20 to 80. In anexemplary embodiment, the parallelogram has one set of opposite anglesthat are approximately about 60 degrees each.

The memory cell subarray 100 is filled with memory cells 102. The memorycells 102 are preferably nonvolatile memory cells each comprising apillar shaped current steering element and a resistivity switchingelement arranged in series. However, other types of volatile ornonvolatile memory cells may also be used. The cells are surrounded by adielectric material 107. The dielectric material 107 is an insulator,for example, silicon dioxide. Other insulating materials, such assilicon nitride, etc., may also be used. The pillar shaped currentsteering element is preferably a diode. For example, a substantiallycylindrical shaped diode of the type described in U.S. Pat. No.6,951,780, incorporated herein by reference in its entirety. Other diodeshapes, such as rectangular diodes, and other steering elements, such astransistors, may also be used. The cells may be one-time programmable(OTP) or re-writable cells of various types. Examples of the resistivityswitching element in the cell includes antifuse, fuse, polysiliconmemory effect cell, metal oxide memory, switchable complex metal oxide,graphene layers, carbon nanotube memory, phase change material memory,conductive bridge element, or switchable polymer memory. In analternative configuration, the diode itself may comprise both thesteering and the resistivity switching elements. In this case, the cellmay include only the diode or the diode in combination with a secondresistivity switching element, such as the antifuse.

The memory cells 102 are typically in a pillar configuration disposedbetween a top and bottom conductor. The general shape of the pillars istypically cylindrical though the pillar can have non-circular crosssectional shapes, such as oval, rectangular or other polygonal shapes.For example, the pillars may comprise an elliptic cylinder, an obliquecylinder, a generalized cylinder, a prism, or a hexagonal prism. Thegeometric description of the general shape of a memory cell is notlimiting; persons of skill in the art will recognize that a memory cellis not restricted to any specific shape or construction.

The memory cells 102 are arranged in a substantially hexagonal patternwhich is contained by the subarray boundary 105. A hexagonal pattern hasthree axes of symmetry, in the same plane, about a point the array. Thethree axes are separated by substantially 60 degrees from one another.Hence, the memory cells 102 are arranged on a hexagonal grid which isalso known as hexagonal tiling, bitruncated hexagonal tiling, oromnitruncatcd hexagonal tiling.

FIG. 2 shows a diagram of a hexagonal pattern. The hexagonal patternconsists of a repeating pattern of seven nonvolatile memory cells havinga central nonvolatile memory cell 240 surrounded by six othernonvolatile memory cells 250 arranged in a hexagonal layout around thecentral nonvolatile memory cell 240. The hexagonal pattern has threeaxes of symmetry: a first axis 210, a second axis 220, and a third axis230. The first axis 210, the second axis 220, and the third axis 230 areseparated by substantially 60 degrees from one another.

Referring again to FIG. 1, the detail view of the memory cell subarrayis described. The detail view shows a first memory cell 110, a secondmemory cell 120, and a third memory cell 130. The first memory cell 110and the second memory cell 120 are separated by a first distance 140.The second memory cell 120 and the third memory cell 130 are separatedby a second distance 150. The first memory cell 110 and the third memorycell 130 are separated by a third distance 160. The first distance 140,the second distance 150, and the third distance 160 are about equal.Thus, any three adjacent memory cells are equidistant from each otherand are located in a same plane. The half pitch between the first memorycell 110 and the second memory cell 120, the second memory cell 120 andthe third memory cell 130, and the first memory cell 110 and the thirdmemory cell 130 is about 22 nm. However, the half-pitch is notrestricted to 22 nm and may range from about 5 nm to about 65 nm forexample (e.g. 10 nm, 32 nm or 45 nm). Advantageously, hexagonal packingof the memory cells takes only about 87% of the area typically used bythe same number of cells using standard rectangular memory layout.

Referring now to FIG. 3, a top view of the bit line and word line layoutof the memory cell subarray of FIG. 1 in accordance with an exemplaryembodiment is shown. Memory cells are each associated with a bit line310 and a word line 320. The bit line(s) 310 are driven by one or morebit line drivers 330. The word line(s) 320 are driven by a one or moreword line driver(s) 340.

The traces of the bit line 310 and the word line 320 follow thehexagonal pattern/grid described above. Hence the word line 320 is about60 degrees off of the bit line 310 when viewed from the top perspective.Thus, the word line(s) cross the bit line(s) at an angle of about 60degrees. An exemplary memory cell 370 is depicted on the intersection ofa bit line and a word line, where the pillar shaped cell extends intothe page of the drawing. It should be noted that the bit line(s) 310 andthe word line(s) 320 are usually on different layers of the memorydevice. Additionally, the bit line(s) 310 and/or the word line(s) 320can be shared between different layers or levels of memory cells in athree dimensional array of memory cells. It should also be noted thatthe half-pitch of the bit lines and the word lines is about 0.87 timesthe half pitch of the memory cells.

Referring now to FIG. 4A, a top view of an array of memory subarrays inaccordance with an exemplary embodiment is shown. A plurality ofsubarrays, such as four or more subarrays, can be constructed over asubstrate, such as a die 400. The substrate may comprise a semiconductorsubstrate, such as a silicon or compound semiconductor substrate, or anon-semiconductor substrate, such as a glass, ceramic, plastic, metal,etc., substrate. The die 400 has an integrated circuit edge 405. Inorder to optimize layout, two types of subarray are used—a firstsubarray 410 and a second subarray 415. An example of the first subarray410 and the second subarray 415 layout are shown in FIG. 4B. The firstsubarray 410 is shaped like a parallelogram with one set of 60 degreeopposite angles. The second subarray 415 is shaped like a parallelogramwith one set of 60 degree opposite angles; however, the layout of thesecond subarray 415 is the mirror of the first subarray 410. Hence, twoof the sides (i.e., the vertical sides in FIG. 4B) of the first subarray410 and two of the sides of the second subarray 415 are parallel witheach other. The non-parallel sides (i.e., diagonal sides) of onesubarray extend about 120 degrees apart from the respective sides of theother subarray. Thus, adjacent subarrays form a substantial mirror imageof each other about a mirror plane extending parallel to the parallelsides (i.e., vertical sides in FIG. 4B) of the adjacent subarrays.

The first subarray 410 and the second subarray 415 are each composed ofa level of a plurality of nonvolatile memory cells and an associatedplurality of bit lines and word lines that connect to the memory cells.The bit lines of the first subarray 410 and the bit lines of the secondsubarray 415 are parallel. The word lines of the first subarray 410 andthe word lines of the second subarray 415 extend in respectivedirections which are about 120 degrees apart. It should be noted thatthe word lines and bit lines may be reversed, such that the word linesof adjacent arrays are parallel and the bit lines of the adjacent arraysextend in directions which are about 120 degrees apart.

The word lines of the first subarray 410 and the word lines of thesecond subarray 415 are driven by a plurality of word line drivercircuits 420. An example of the plurality of word line driver circuits420 layout is shown in FIG. 4C. The plurality of word line drivercircuits 420 are word line drivers matched to the type of memory cell.For example, the word line drivers can be of the voltage forcing type.Additionally, the word line drivers can have dual use devices asdescribed in more detail in U.S. Pat. No. 6,856,572, which herebyincorporated by reference in its entirety. The plurality of word linedriver circuits 420 can be shared amongst subarrays and amongst memorycell levels within a subarray. In one embodiment half the word lines aredriven from the left side of the subarray and the other half are drivenfrom the right side of the subarray.

The bit lines of the first subarray 410 and the bit lines of the secondsubarray 415 are driven by a first plurality of bit line driver circuits430 and a second plurality of bit line driver circuits 435. An exampleof the first plurality of bit line driver circuits 430 and the secondplurality of bit line driver circuits 435 layout is shown in FIG. 4D.The first plurality of bit line driver circuits 430 is staggered tomatch the non-parallel edge of the first subarray 410. The secondplurality of bit line driver circuits 435 is staggered to match thenon-parallel edge of the second subarray 415. Staggering means that thelayout of the circuit looks like a staircase; that is, the circuit ischunked into blocks to follow a skewed path, such as a diagonal edge ofa subarray which extends at an angle of about 60 degrees from theadjacent edge of the same subarray. The bit line driver circuits arestaggered in order to transition from the skew edge of the memorysubarrays to the integrated circuit edge 405. The first plurality of bitline driver circuits 430 and the second plurality of bit line drivercircuits 435 are bit line drivers matched to the type of memory cell.For example, the bit line drivers can be of the current sensing type.Additionally, the bit line drivers can have separate read and writelines or be bidirectional. The first plurality of bit line drivercircuits 430 and the second plurality of bit line driver circuits 435can be shared amongst subarrays and amongst memory cell levels within asubarray.

A plurality of the first subarrays 410 and the second subarrays 415 areconstructed over the substrate, such as the die 400 in a substantiallyrectangular array so that outline of the rectangular array follows theintegrated circuit edge 405. The plurality of word line driver circuits420 are preferably located on a different level from the subarrays ofthe nonvolatile memory cells, such as below the subarrays, for examplein or on a surface of substrate such as a silicon wafer. Each the wordline driver circuit 420 preferably occupies an area that straddles aprojection of the parallel (i.e., vertical) sides respective subarrays.Preferably, the central portions of the word line driver circuits areexposed in the space between adjacent overlying memory subarrays, whileedge portions of the word line driver circuits are located directlybelow the overlying memory subarrays, as shown in FIG. 4A. However,other suitable layout configurations may also be used. The plurality ofword line driver circuits 420 are connected to the word lines of thesubarrays by vertical word line connectors. The vertical word lineconnectors are also known as conductor filled vias or zias. The ziasallow multiple levels of subarrays to be connected to the same pluralityof word line driver circuits. The word zias can also be shared amongstsubarrays.

The bit line driver circuits are also located on a different level fromthe subarrays of nonvolatile memory cells, such as below the subarrays,for example in or on a surface of substrate such as a silicon wafer.Each the bit line driver circuit occupies a staggered area thatpreferably straddles a projection of the diagonal sides over theoverlying subarrays. First plurality bit line driver circuits 430 arelocated below respective first subarrays 410 while a second plurality ofbit line driver circuits 435 are located below the second subarrays 415.Preferably, the central portions of the bit line driver circuits 430,435 are exposed in the space between adjacent overlying memory subarrays410, 415, respectively, while edge portions of the bit line drivercircuits are located directly below the overlying memory subarrays, asshown in FIG. 4A. However, other suitable layout configurations may alsobe used. The first plurality of bit line driver circuits 430 and thesecond plurality of bit line driver circuits 435 are connected to thebit lines of the subarrays by vertical word line connectors, such aszias. The zias allow multiple levels of subarrays to be connected to thesame plurality of bit line driver circuits. The bit zias can also beshared amongst subarrays. The drivers are preferably located on all foursides of each subarray, with a substantially equal number of drivers onopposite sides of each subarray.

Referring now to FIG. 5, a perspective view of a memory subarray inaccordance with an exemplary embodiment is shown to illustrate the threedimensional aspects of an array of memory subarrays. A three dimensionalarray of subarrays 500 is depicted on a die 510. The three dimensionalarray of subarrays 500 has a first memory subarray 520 in a first leveland a second memory subarray 525 in a second level. The first memorysubarray 520 is located directly above the second memory subarray 525.The first memory subarray level 520 is shaped substantially like aparallelogram. The first memory subarray 520 has two opposing sides thatextend about perpendicular relative to a die edge 515. The other twosides of the first memory subarray 520 extend non-parallel, such as atan angle of about 30 degrees relative to the die edge 515. The secondmemory subarray 525 is shaped similar to the first memory subarray 520.

The first memory subarray 520 and the second memory subarray 525 bothcontain a plurality of memory cells organized in a hexagonal pattern. Anexemplary memory cell 530 is shown. The memory cells of the first memorysubarray 520 and the second memory subarray 525 are associated with bitlines 540 and word lines 550. The bit lines 540 and word lines 550connect to the individual memory cells. It should be noted that insteadof the configuration shown in FIG. 5, the bit lines may be located beloweach subarray and the word lines may be located above each subarray ifdesired. The word lines extend substantially parallel to diagonal sidesof each subarray and the bit lines extend substantially parallel to theother sides of each subarray. The bit lines 540 are connected tovertical bit line connections 545, such as bit line zias. In a preferredembodiment, bit lines from subarray 520 have separate bit line zias fromthe bit line zias connected to bit lines on sub array 525. FIG. 5 showsseparate bit line zias connected to bit lines 540 in subarrays 520 and525. In this case, each block (i.e., stepped portion) 560 shown in FIG.5 comprises at least two bit line drivers. However, each bit line drivermay be located in a separate block. Preferably, in a vertical group ofsubarrays that share word line zias 555 between word lines 550, the bitlines 540 do not share zias 545 to uniquely address cells. However, bitlines 540 from adjacent subarrays on the same level can still share bitline zias 545. As noted above, the word lines 550 are connected tovertical word line connections 555, such as word line zias. In apreferred embodiment, the word line zias are shared, as described, forexample in U.S. Pat. No. 7,177,169 which is incorporated herein byreference in its entirety. These word line zias extend along side thefirst memory subarray 520 and the second memory subarray 525 and in thespace between adjacent subarrays in the same level. The bit line ziasextend between the diagonal sides of adjacent subarrays and the wordline zias extend between the other sides of the adjacent subarrays. Asnoted above, the word lines and the bit lines may be reversed and thusthe word line and bit line zia designations may be reversed as well ifdesired.

The vertical bit line connections 545 are driven by a bit line driver560. The vertical word line connections 555 are driven by a word linedriver 570. The bit line driver 560 and the word line driver 570 can belocated at least partially underneath the first memory subarray 520 andthe second memory subarray 525, as described in more detail above withrespect to FIG. 4A. Alternatively, only the word line drivers may belocated underneath the first memory subarray and the bit line driversare not located underneath the first memory subarray.

Advantageously, by placing the bit line driver circuits and the wordline driver circuits on a different level than the memory subarrays, thememory subarrays can be packed together more tightly thereby reducingthe die space needed for a memory device. Additionally, by transitioningthe skewed, non-parallel edge of a memory subarray to be parallel withthe integrated circuit edge, outside devices can more easily interfacewith the die.

Forming Subarray Using Triple Exposure

A fabrication method of a single memory level using triple exposureaccording to a second embodiment of the invention will be described indetail. While the method is preferably used to form the nonvolatilememory array described in the first embodiment, the method may be usedto form any other volatile or nonvolatile memory array, as well as otherdevices, such as logic, display, photovoltaic, lighting, magnetic datastorage, etc. devices. Furthermore, the array of the first embodimentmay be formed using methods other than triple exposure, such as byconventional single exposure photolithography. Additional memory levelscan be stacked, each monolithically formed above the one below it. Inthis embodiment, a polycrystalline semiconductor diode will serve as thememory cell. Alternatively, the memory cell can be antifuse, fuse, diodeand antifuse arranged in a series, polysilicon memory effect cell, metaloxide memory, switchable complex metal oxide, carbon nanotube memory,phase change material memory, conductive bridge element, or switchablepolymer memory.

The formation of the memory device begins with a substrate. Thissubstrate can be any semiconducting substrate as known in the art, suchas monocrystalline silicon, IV-IV compounds including silicon-germaniumor silicon-germanium-carbon, III-V compounds, II-VII compounds,epitaxial layers over such substrates, or any other semiconductormaterial or non-semiconductor material, such as metal, glass, ceramic,plastic, etc. The substrate may include integrated circuits fabricatedtherein or thereon.

An insulating layer is formed over substrate. The insulating layer canbe silicon oxide, silicon nitride, high-dielectric film, Si—C—O—H film,or any other suitable insulating material.

Next, the word lines are formed over the substrate and the insulatinglayer. An adhesion layer may be included between the insulating layerand the word line layer to help the word line layer adhere to insulatinglayer. If the overlying word line layer is tungsten, titanium nitride ispreferred as adhesion layer. If desired, bit lines rather than wordlines may be formed first.

The next layer to be deposited is a word line layer. The word line layercan comprise any conducting material known in the art, such as tungsten,or other materials, including tantalum, titanium, copper, cobalt, oralloys thereof.

Referring to FIG. 7, a diagram showing a double exposure process of bitlines and word lines in accordance with an exemplary embodiment isshown. Once all the layers that will form the word lines have beendeposited, the layers are patterned. Preferably, the word lines arepatterned using double exposure and etched using any suitable maskingand etching process. However, a single exposure patterning process, ordouble patterning process, or complementary patterning process may alsobe used instead. A photoresist layer is deposited on the word linelayer. A positive or negative photoresist layer may be used. Preferably,a negative resist is used in which the imaged areas are renderedinsoluble. The photoresist layer is exposed using a first mask to formfirst exposed regions which will be used to etch a first set of wordlines 710 which will be driven by word line drivers 750. If a negativephotoresist is used, then the exposed regions are rendered insoluble.Then, the photoresist layer is exposed again using a second mask to formsecond exposed regions which will be used to etch a second set of wordlines 720 which are adjacent to the first set of word lines 710. Otherfeatures may also be patterned along with the word lines. After thephotoresist is developed and patterned, the layers are etched using thepatterned photoresist as a mask. The photoresist is then removed usingstandard process techniques. The word lines could be formed by aDamascene method instead.

Next a dielectric material is deposited over and between word lines.Dielectric material can be any known electrically insulating material,such as silicon oxide, silicon nitride, or silicon oxynitride. In apreferred embodiment, silicon dioxide is used as dielectric material.

Finally, excess dielectric material on top of the word lines is removed,exposing the tops of the word lines separated by dielectric material,and leaving a substantially planar surface. This removal of dielectricoverfill to form planar surface can be performed by any process known inthe art, such as chemical mechanical polishing (CMP) or etchback. Anetchback technique that may advantageously be used is described inRaghuram et al., U.S. application Ser. No. 10/883,417, “Non-selectiveUnpatterned Etchback to Expose Buried Patterned Features,” filed Jun.30, 2004, which issued as U.S. Pat. No. 7,307,013, and herebyincorporated by reference. At this stage, a plurality of substantiallyparallel word lines have been formed above the substrate.

Next, vertical pillars will be formed above completed word lines.Preferably a barrier layer is deposited as the first layer afterplanarization of the word lines. Any suitable material can be used inthe barrier layer, including tungsten nitride, tantalum nitride,titanium nitride, or combinations of these materials. In a preferredembodiment, titanium nitride is used as the barrier layer. Where thebarrier layer is titanium nitride, it can be deposited in the samemanner as the adhesion layer described earlier.

Next, a thin film layer (or layers) of semiconductor material that willbe patterned into pillars is deposited. The semiconductor material canbe silicon, germanium, a silicon-germanium alloy, or other suitablesemiconductors, or semiconductor alloys. For simplicity, thisdescription will refer to the semiconductor material as silicon, but itwill be understood that the skilled practitioner may select any of theseother suitable materials instead.

In an exemplary embodiment, the pillar comprises a semiconductorjunction diode. The term junction diode is used herein to refer to asemiconductor device with the property of non-ohmic conduction, havingtwo terminal electrodes, and made of semiconducting material which isp-type at one electrode and n-type at the other. Examples include p-ndiodes and n-p diodes, which have p-type semiconductor material andn-type semiconductor material in contact, such as Zener diodes, andp-i-n diodes, in which intrinsic (undoped) semiconductor material isinterposed between p-type semiconductor material and n-typesemiconductor material.

First, a bottom heavily doped region can be formed by any deposition anddoping method known in the art. The silicon can be deposited and thendoped, but is preferably doped in situ by flowing a donor gas providingn-type dopant atoms, for example phosphorus, during deposition of thesilicon. The heavily doped region is preferably between about 100 andabout 800 angstroms thick.

Next, an intrinsic layer can be formed by any method known in the art.The intrinsic layer can be silicon, germanium, or any alloy of siliconor germanium and has a thickness between about 1100 and about 3300angstroms, preferably about 2000 angstroms.

The intrinsic layer and heavily doped region just deposited, along withthe underlying barrier layer, will be patterned and etched to formpillars. Pillars should have about the same pitch and about the samewidth as the word lines below, such that each pillar is formed on top ofa word line. Some misalignment can be tolerated. P-type diode regionscan be formed at this time or after the patterning step as described inmore detail below.

The pillars can be formed using any suitable masking and etchingprocess. Referring now to FIG. 6, a diagram showing a triple exposureprocess of a memory cell array in accordance with an exemplaryembodiment is shown. First, a second photoresist layer is formed overthe surface of the pillar material, such as the semiconductor layer(s).The photoresist can be a negative photoresist or a positive photoresist.An exemplary process using negative photoresist is now described withreference to FIG. 6. In a subarray area 605, a first exposure of thephotoresist layer is performed using a first mask to form first exposedregions 640 in the photoresist layer. Next, a second exposure of thephotoresist layer is performed using a second mask to form secondexposed regions 650 in the photoresist layer. Finally, a third exposureof the photoresist layer is performed using a third mask to form thirdexposed regions 660 in the photoresist layer, such that each adjacentfirst 640, second 650 and third exposed regions 660 are approximatelyequidistant from each other. The first, second, and third exposure havecreated a hexagonal pattern 610 in the photoresist which can now be usedto form a plurality of pillar shaped devices arranged in a substantiallyhexagonal pattern. The hexagonal pattern 610 comprises a repeatingpattern of seven pillars having a central pillar surrounded by six otherpillars arranged in a hexagonal layout around the central pillar. Afterthe photoresist is developed, the pillar layer is etched using thepatterned photoresist as a mask. The pillars are preferably cylindrical,but may have other shapes as described herein.

Alternatively, a hard mask of some other material, for example silicondioxide, silicon nitride, tungsten or tungsten oxide, can be formed ontop of the semiconductor layer stack, with bottom antireflective coating(BARC) on top, then patterned and etched. Similarly, a dielectricantireflective coating (DARC) can be used as a hard mask. Thesemiconductor layers are patterned using the hard mask as a mask beforeor after the removal of the photoresist layer.

Alternatively a positive photoresist can be used to pattern the pillars.First, second and third exposures of the photoresist expose the positivephotoresist in locations for representative pillars 640, 650, 660 in anhexagonal pattern. The photoresist is then developed and forms holes inthe locations for representative pillars 640, 650, 660 in a hexagonalpattern. Any suitable image reversal process is then used to create etchresistant shapes in the holes. For example, a hard mask material or afiller material is formed over the photoresist layer and in the holes inthe photoresist layer. The hardmask material or the filler material isthen planarized such that it remains only in the holes in thephotoresist layer. For example, the hardmask layer may be planarized byCMP or etchback, while the filler material may be formed by spin coatinga filler material slurry over the photoresist such that it settles onlyin the holes in the photoresist layer. If the hardmask material, such asan insulating hardmask material (for example silicon oxide, tungstenoxide or silicon nitride) or a conductive hardmask material (for exampletungsten), is used to fill the holes in the photoresist, then thehardmask shapes are used as a mask to pattern (i.e., etch) theunderlying semiconductor layers. As in the preceding exemplary process,the semiconductor layers are patterned using the hardmask as a maskbefore or after the removal of the patterned photoresist layer. If afiller material, such as an organic filler material, such as a siliconcontaining spin-on coating described in U.S. application Ser. No.11/864,205 to T. Chen et al., filed on Sep. 28, 2007 and incorporatedherein by reference in its entirety is used, then a hardmask layer canbe located between the filler material and the underlying semiconductorlayers. The filler material shapes are used as a mask to pattern thehardmask layer into shapes. The hardmask shapes are then used to as amask to pattern the underlying semiconductor layers.

After the semiconductor layers are patterned, a dielectric material isdeposited over and between the semiconductor pillars, filling the gapsbetween them. The dielectric material can be any known electricallyinsulating material, such as silicon oxide, silicon nitride, or siliconoxynitride. In a preferred embodiment, silicon dioxide is used as theinsulating material.

Next the dielectric material on top of the pillars is removed, exposingthe tops of pillars separated by dielectric material, and leaving asubstantially planar surface. This removal of dielectric overfill can beperformed by any process known in the art, such as chemical mechanicalpolishing (CMP) or etchback. After CMP or etchback, ion implantation isperformed, forming heavily doped p-type top region of the diode. Thep-type dopant is preferably boron or BCl₃. This implant step completesformation of the diodes. In the diodes just formed, the bottom heavilydoped regions are n-type while the top heavily doped regions are p-type.

Finally, the bit lines are formed in the same manner as the word lines,for example by depositing an adhesion layer, preferably of titaniumnitride, and a bit line layer, preferably of tungsten. Referring againto FIG. 7, the bit line layer and adhesion layer are then patternedusing double exposure and etched using any suitable masking and etchingprocess. However, a single exposure method may be used instead. In oneembodiment, a third photoresist layer is deposited on the bit linelayer. The photoresist layer is exposed using a first mask to form firstexposed regions which will be used to etch a first set of bit lines 730which will be driven by bit line drivers 760. If a negative photoresistis used, then the exposed regions are rendered insoluble. Then, thephotoresist layer is exposed again using a second mask to form secondexposed regions which will be used to etch a second set of bit lines 740which are adjacent to the first set of bit lines 730. Other features mayalso be patterned along with the bit lines. After the photoresist isdeveloped, the conductive layers are etched using the photoresistpattern as a mask, and then the photoresist pattern removed usingstandard process techniques. As noted above, the order of formation ofthe bit lines and the word lines can be reversed.

Next a dielectric material is deposited over and between the bit lines.The dielectric material can be any known electrically insulatingmaterial, such as silicon oxide, silicon nitride, or silicon oxynitride.In a preferred embodiment, silicon oxide is used as this dielectricmaterial. The bit lines cross the word lines at an angle of about 60degrees. Advantageously, triple exposure allows devices with smallerhalf-pitches to be formed which allows full use of the reduced scalingfactor of double exposed lines. Moreover, the hexagonally packed memorycells require less die area. Additionally, devices with smallerhalf-pitches use smaller die sizes. The use of triple exposure to forman array of cells in a hexagonal configuration allows the array patternto be relaxed by a factor of 1.73 compared to a rectangular arrayconfiguration formed by conventional single exposure typephotolithography.

Formation of a first memory level has been described. Additional memorylevels can be formed above this first memory level to form a monolithicthree dimensional memory array. In some embodiments, conductors can beshared between memory levels; i.e. the top array lines for one levelwould serve as the bottom array lines of the next memory level. In otherembodiments, an interlevel dielectric is formed above the first memorylevel, its surface planarized, and construction of a second memory levelbegins on this planarized interlevel dielectric, with no sharedconductors.

A monolithic three dimensional memory array is one in which multiplememory levels are formed above a single substrate, such as a wafer, withno intervening substrates. The layers forming one memory level aredeposited or grown directly over the layers of an existing level orlevels. In contrast, stacked memories have been constructed by formingmemory levels on separate substrates and adhering the memory levels atopeach other, as in Leedy, U.S. Pat. No. 5,915,167, “Three dimensionalstructure memory.” The substrates may be thinned or removed from thememory levels before bonding, but as the memory levels are initiallyformed over separate substrates, such memories are not true monolithicthree dimensional memory arrays.

A monolithic three dimensional memory array formed above a substratecomprises at least a first memory level formed at a first height abovethe substrate and a second memory level formed at a second heightdifferent from the first height. Three, four, eight, or indeed anynumber of memory levels can be formed above the substrate in such amultilevel array.

An alternative method for forming a similar array in which conductorsare formed using Damascene construction is described in Radigan et al.,U.S. patent application Ser. No. 11/444,936, “Conductive Hard Mask toProtect Patterned Features During Trench Etch,” filed May 31, 2006,assigned to the assignee of the present invention and herebyincorporated by reference. The methods of Radigan et al. may be usedinstead to form an array according to the present invention.

Forming A Subarray Using Quadruple Exposure

Alternatively, in a third embodiment, the pillars are formed in arectangular grid using four exposures. Referring now to FIG. 8, adiagram showing a quadruple exposure process of a memory cell array inaccordance with an exemplary embodiment is shown. First a photoresistlayer is formed over the surface of the pillar material, such as thesemiconductor layers of the prior embodiments. The photoresist can be anegative photoresist or a positive photoresist. In a rectangularsubarray area 810, a first exposure of an exemplary negative photoresistlayer is performed using a first mask to form first exposed regions 820in the photoresist layer. Next, a second exposure of the photoresistlayer is performed using a second mask to form second exposed regions830 in the photoresist layer. A third exposure of the photoresist layeris performed using a third mask to form third exposed regions 840 in thephotoresist layer. Finally, a fourth exposure of the photoresist layeris performed using a fourth mask to form fourth 850 exposed regions inthe photoresist layer, such that any set of adjacent first 820, second830, third 840, and fourth exposed regions 850 form a substantiallyrectangular or square pattern. The first, second, third, and fourthexposure create a grid pattern 805 in the photoresist layer afterdevelopment and patterning of the photoresist. The first, second, third,and fourth mask can instead be a shared mask where the exposure for thesecond, third, and fourth exposure are made after shifting the locationof the mask in a lithography tool by the appropriate amount. Thephotoresist pattern is then used to form a plurality of pillar shapeddevices arranged in a substantially grid pattern. After the photoresistis developed, the pillar layer is etched. Consequently, the word linesand bit lines are aligned in a grid (i.e. crossing at about 90 degreesapart).

The bit line layer and word line layer (on either side of the pillarlayer) are formed using double exposure. During word line formation, thephotoresist on top of the word layer material is exposed using a firstmask to image a first set of word lines 890. The photoresist is exposedagain using a second mask to image a second set of word lines 880 whichare adjacent to the first set of word lines 890. Likewise, during bitline formation, the photoresist on top of the bit layer material isexposed using a third mask to image a first set of bit lines 860. Thephotoresist is exposed again using a fourth mask to image a second setof bit lines 870 which are adjacent to the first set of bit lines 860.

Advantageously, quadruple exposure allows devices with smallerhalf-pitches to be formed which allows full use of the reduced scalingfactor of double exposed lines. Additionally, devices with smallerhalf-pitches use smaller die sizes.

Forming a Subarray Using Self-Assembling Polymers

Alternatively, in a fourth embodiment, the pillar devices, such as thedevices described in the first embodiment or other devices, are formedusing a self-assembling material instead of a photoresist. Self-assemblyis the spontaneous organization of materials into regular patterns.Self-assembling materials are suitable for forming a well-defined latentimage. Unlike photoresists, however, self-assembling material canautonomously form regular patterns at dimensions not achievable bylithographic means. An example of self-assembling material is describedby Black, et al., “Polymer self assembly in semiconductormicroelectronics,” IBM J. Res. & Dev., Vol. 51 No. 5, Sep. 2007, whichis incorporated herein by reference in its entirety.

FIG. 9 is a diagram showing a self-assembly polymer process of a memorycell array in accordance with the fourth embodiment and FIG. 10 is aflowchart showing a self-assembly polymer process of a memory cell arrayin accordance with the fourth embodiment. In a forming operation 1010, alayer of self-assembling material, such as diblock copolymers likepolystyrene (PS) and polymethylmethacrylate (PMMA): (PS:PMMA) orpolystyrene (PS) and poly(ethylene oxide): PS-b-(PEO+PMS), is formedover the surface of the pillar material. A subarray boundary 905 isfilled with a self-assembling material or layer 910. For example, theboundary may have a parallelogram shape described above. The boundarymay comprise the edge of a layer on which the self-assembling materialis deposited or a wall of a groove in an underlying layer.

In an assembly operation 1020, the self-assembling layer forms an arrayof holes in an hexagonal pattern. Electromagnetic fields may be used toassist formation of the hexagonal pattern. Holes 902 in theself-assembling material 910 run all the way through to the pillarlayer; however, a brief etching may be needed to ensure that the holes902 extend all the way through the self-assembly material 910 to thepillar layer.

Referring again to FIG. 10, in a hard mask operation 1030, a hard mask,such as tungsten oxide, silicon oxide, silicon nitride, etc. isdeposited over the surface of the self-assembling material and into theholes of the self-assembling material. In an etching operation 1040, anisotropic back etch is used to remove the hard mask material that iscovering the self-assembling material, leaving the hard mask material inthe holes of the self-assembling material. Alternatively, CMP could beused to remove excess hard mask material. Hard mask disks or cylindersnow remain in the holes of the self-assembling material. An alternativeprocess for forming a hard mask pattern in the holes of the selfassembly layer deposits a spin on silicon containing material in theholes and etches away the self-assembly layer by dry etching with alarge etch rate ratio between the silicon containing material and theself-assembly layer, as is described in more detail in U.S. applicationSer. No. 11/864,205 to T. Chen et al., filed on Sep. 28, 2007 and herebyincorporated by reference in its entirety.

In a clean-up operation 1050, the self-assembling material is removedfrom the surface of the pillar material. Now, a plurality of hard maskdisks in a hexagonal pattern are left on top of the pillar material. Ina pillar etching operation 1060, the pillar material is etched using thehard mask disks thereby forming pillar shaped devices. The hard maskdisks can be removed after the etching step or left in the final device.

The self-assembling material can also be designed to form a rectangulargrid. The self-assembling material itself may be used as a mask forexposing an underlying photoresist. Additionally, the word lines (orwhatever conductive layer, such as bit lines, that has been formedfirst) may have current or charge applied in order to promote holeformation in line with the word lines. Indeed, the word lines and bitlines may also be formed using self-assembling material.

Advantageously, using self-assembling material to form pillar shapesallows devices with smaller half-pitches to be formed which allows fulluse of the reduced scaling factor of double exposed lines. Additionally,devices with smaller half-pitches use smaller die sizes.

Triple exposure, quadruple exposure, and use of self-assembling materialare not restricted to memory devices or semiconductor devices ingeneral. For example, the above described methods can be used to createlight emitting devices in liquid crystal displays, magnetic storageelements on a hard disk drive, or any other device that is formed as apillar-like shape. Hence, the substrates used could also be glass,metal, ceramics or plastics. The term substrate may also include thinfilm materials formed on top of other substrates.

While the invention has been largely described with respect to theembodiments set forth above, the invention is not necessarily limited tothese embodiments. For example, the instant invention can also beapplied to three-dimensional memory arrays configured as a plurality oflevels, where word lines and/or bit lines are shared between levels,such as segmented word line arrays, including, but not limited to: (1)the memory described in U.S. Pat. No. 6,034,882 issued on Mar. 7, 2000and U.S. Pat. No. 6,185,122 issued on Feb. 6, 2001, to Mark G. Johnson,et al., both commonly assigned herewith; (2) the memory array describedin U.S. patent application Ser. No. 09/560,626 filed on Apr. 28, 2000,in the name of N. Johan Knall and commonly assigned herewith; (3) thememory array described in U.S. patent application Ser. No. 09/814,727filed on Mar. 21, 2001, in the name of N. Johan Knall and Mark G.Johnson and commonly assigned herewith; The memory described in“Three-Dimensional Memory Array Incorporating Serial Chain Diode Stack”by Kleveland, et al, U.S. patent application Ser. No. 09/897,705, filedon Jun. 29, 2001; the memory described in U.S. Pat. No. 7,177,169referenced above; and the memory described in U.S. patent applicationSer. No. 10/185,508 by Cleeves, filed Jun. 27, 2002, entitled “ThreeDimensional Memory”, each of which is hereby incorporated by reference.

As used herein, a passive element memory array includes a plurality of2-terminal memory cells, each connected between an associated X-line andan associated Y-line. Such a memory array may be a two-dimensional(planar) array or may be a three-dimensional array having more than oneplane of memory cells. Each such memory cell has a non-linearconductivity in which the current in a reverse direction (i.e., fromcathode to anode) is lower than the current in a forward direction.Application of a voltage from anode to cathode greater than aprogramming level changes the conductivity of the memory cell. Theconductivity may decrease when the memory cell incorporates a fusetechnology, or may increase when the memory cell incorporates anantifuse technology. A passive element memory array is not necessarily aone-time programmable (i.e., write once) memory array. The memory cellmay incorporate a reprogrammable memory material for which theconductivity may decrease or increase after application of a suitableelectrical pulse.

Such passive element memory cells may generally be viewed as having acurrent steering element such as a diode directing current in adirection and another component which is capable of changing its state(e.g., a fuse, an antifuse, a capacitor, a resistive element, etc.). Inalternative configurations, the memory element is a diode-like structurehaving a p+ region separated from an n− region by an antifuse element.When the antifuse element is programmed, the p+ region is electricallyconnected to the n− region and forms a diode. The programming state ofthe memory element can be read by sensing current flow or voltage dropwhen the memory element is selected. In an organic PEMA embodiment, thememory element is a diode-like structure having an anode regionseparated from a cathode region by an organic material layer whoseconductivity changes as electrons are injected into the layer.

Preferably, the memory cells are comprised of semiconductor materials,as described in U.S. Pat. No. 6,034,882 to Johnson et al., U.S. Pat. No.5,835,396 to Zhang, U.S. patent application Ser. No. 09/560,626 byKnall, and U.S. patent application Ser. No. 09/638,428 by Johnson, eachof which are hereby incorporated by reference. Specifically an antifusememory cell may be used. Other types of memory arrays that are stackableover support circuits, such as MRAM and organic passive element arrays,can also be used. MRAM (magnetoresistive random access memory) is basedon magnetic memory elements, such as a magnetic tunnel junction (MTJ).MRAM technology is described in “A 2556 kb 3.0 V ITIMTJ NonvolatileMagnetoresistive RAM” by Peter K. Naji et al., published in the Digestof Technical Papers of the 2001 IEEE International Solid-State CircuitsConference, ISSCC 2001/Session 7/Technology Directions: AdvancedTechnologies/7.6, Feb. 6, 2001 and pages 94-95, 404-405 of ISSCC 2001Visual Supplement, both of which are hereby incorporated by reference.Certain passive element memory cells incorporate layers of organicmaterials including at least one layer that has a diode-likecharacteristic conduction and at least one organic material that changesconductivity with the application of an electric field. U.S. Pat. No.6,055,180 to Gudensen et al. describes organic passive element arraysand is also hereby incorporated by reference. Memory cells comprisingmaterials such as phase-change materials and amorphous solids can alsobe used. See U.S. Pat. No. 5,751,012 to Wolstenholme et al. and U.S.Pat. No. 4,646,266 to Ovshinsky et al., both of which are herebyincorporated by reference. Memory cells comprising resistance changematerials including transition metal oxides, as described in more detailin U.S. patent application Ser. No. 11/287,452 by Herner, et al. whichis hereby incorporated by reference, and carbon nanotube layers, whichmay be formed as described in U.S. Patent Pub 20050269553 by Sen, Rahul;et al. which is hereby incorporated by reference, or a switchableresistance material comprising several atomic layers of graphene canalso be used.

Based upon the teachings of this disclosure, it is expected that one ofordinary skill in the art will be readily able to practice the presentinvention. The descriptions of the various embodiments provided hereinare believed to provide ample insight and details of the presentinvention to enable one of ordinary skill to practice the invention.Although certain supporting circuits (e.g., decoders, sensing circuits,multiplexers, input/output buffers, etc.) are not specificallydescribed, such circuits are well known, and no particular advantage isafforded by specific variations of such circuits in the context ofpracticing this invention. Moreover, it is believed that one of ordinaryskill in the art, equipped with the teaching of this disclosure, will beable to carry out the invention, including implementing various controlcircuits inferred but not specifically described herein, using wellknown circuit techniques and without undue experimentation. Nonetheless,additional details of bias conditions, bias circuits, and layer decodercircuits particularly suitable for a three-dimensional memory array ofwrite-once anti-fuse passive element memory cells are described in U.S.application Ser. No. 09/897,771, entitled “Method and Apparatus forBiasing Selected and Unselected Array Lines When Writing a MemoryArray”, by Roy E. Scheuerlein, filed on Jun. 29, 2001, and in“Three-Dimensional Memory Array Incorporating Serial Chain Diode Stack”by Kleveland, et al, U.S. patent application Ser. No. 09/897,705, filedon Jun. 29, 2001 referred to above, which are both hereby incorporatedby reference in their entirety.

In the above description, an array line is generally shared by twolevels of the memory array (i.e., memory planes). Alternatively, amemory array may be fabricated having two conductors for each plane thatare not shared with other planes. A dielectric layer may be used toseparate each such memory level.

Word lines may also be referred to as row lines or X-lines, and bitlines may also be referred to as column lines or Y-lines. Thedistinction between “word” lines and “bit” lines may carry certainconnotations to those skilled in the art. When reading a memory array,it is assumed by some practitioners that word lines are “driven” and bitlines are “sensed.” Moreover, the memory organization (e.g., data buswidth, number of bits simultaneously read during an operation, etc.) mayhave some association with viewing one set of the two array lines morealigned with data “bits” rather than data “words.” Neither connotationis necessarily intended in this description.

The directionality of X-lines (e.g., which may be shown horizontally)and Y-lines (e.g., which may be shown vertically) is merely convenientfor ease of description of the two groups of crossing lines in thearray. While X-lines are usually orthogonal to Y-lines, such is notnecessarily implied by such terminology. Moreover, the word and bitorganization of a memory array may also be easily reversed, havingY-lines organized as word lines and X-lines organized as bit lines. Asan additional example, portions of an array may correspond to differentoutput bits of given word. Such various array organizations andconfigurations are well known in the art, and the invention in intendedto comprehend a wide variety of such variations.

The embodiments described may refer to a selected word line being drivento a voltage and a selected bit line being sensed in a read mode, andmemory cell anode terminals connected to word lines and cathodeterminals connected to bit lines, but other embodiments are specificallycontemplated. For example, in a three-dimensional (i.e., multi-level)memory array, an adjacent memory plane may be connected similarly (e.g.,a back-to-back diode stack memory array as described in U.S. Pat. No.6,034,882 to Johnson, et al., referred to above), or may reverse thedirectionality of memory cells in the adjacent plane (e.g., a serialchain diode stack memory array as described in U.S. patent applicationSer. No. 09/897,705 by Kleveland, et al., referred to above) so that theanode terminals are connected to bit lines and the cathode terminals toword lines. Consequently, the designations herein of X-lines, wordlines, and row lines, and of Y-lines, bit lines, and column lines areillustrative of the various embodiments but should not be viewed in arestrictive sense, but rather a more general sense. For example, sensingcircuits may be coupled to word lines rather than bit lines, or may beused for both word lines and bit lines, when sensing a current in a wordline rather than in a bit line. For example, it should be appreciatedthat the designations X-line and Y-line for various array lines of amemory array on a serial chain diode stack do not necessarily implywhich terminal of the memory cells (i.e., anode or cathode) is coupledto the particular line, as with a back-to-back diode stack. An X-linemay be coupled to the anode terminal of memory cells in one associatedmemory plane, and may be coupled to the cathode terminal of memory cellsin an adjacent memory plane.

Integrated circuits incorporating a memory array usually subdivide thearray into a sometimes large number of smaller arrays, also sometimesknown as subarrays. As used herein, an array is a contiguous group ofmemory cells having contiguous word and bit lines generally unbroken bydecoders, drivers, sense amplifiers, and input/output circuits. Anintegrated circuit including a memory array may have one array, morethan one array, or even a large number of arrays. An used herein, anintegrated circuit memory array is a monolithic integrated circuitstructure, rather than more than one integrated circuit device packagedtogether or in close proximity, or die-bonded together.

The foregoing details description has described only a few of the manypossible implementations of the present invention. For this reason, thisdetailed description is intended by way of illustration, and not by wayof limitations. Variations and modifications of the embodimentsdisclosed herein may be made based on the description set forth herein,without departing from the scope and spirit of the invention. It is onlythe following claims, including all equivalents, that are intended todefine the scope of this invention.

What is claimed is:
 1. A nonvolatile memory device, comprising: aplurality of nonvolatile memory cells arranged in a substantiallyhexagonal pattern, wherein the nonvolatile memory cells are arranged ina plurality of subarrays which are substantially parallelogram shapedand have a non-square corner, wherein each subarray among the pluralityof subarrays includes a plurality of nonvolatile memory cells arrangedin a substantially hexagonal pattern; wherein each of the plurality ofsubarrays has parallel sides that extend along a first direction and anon-parallel side that adjoins a respective driver circuit block fordriving the subarray; wherein the driver circuit blocks for theplurality of subarrays have a staggered layout such that a layout ofeach driver circuit block is shifted along the first direction from ahorizontal line that is perpendicular to the first direction and passesthrough the non-square corner by a respective lateral offset distance;and the lateral offset distances differ among one another among anentire set of driver circuit blocks that drive the plurality ofsubarrays.
 2. The nonvolatile memory device of claim 1, wherein: theplurality of nonvolatile memory cells comprises a plurality of pillarshaped current steering elements; and the substantially hexagonalpattern comprises a repeating pattern of seven nonvolatile memory cellshaving a central nonvolatile memory cell surrounded by six othernonvolatile memory cells arranged in a hexagonal layout around thecentral nonvolatile memory cell.
 3. The nonvolatile memory device ofclaim 1, wherein the device comprises: a first nonvolatile memory cell,a second nonvolatile memory cell, and a third nonvolatile memory cell;wherein the first nonvolatile memory cell, the second nonvolatile memorycell, and the third nonvolatile memory cell are equidistant from eachother and are located in a same plane.
 4. The nonvolatile memory deviceof claim 3, wherein the first nonvolatile memory cell, the secondnonvolatile memory cell, and the third nonvolatile memory cell have acell half pitch of less than about 32 nm.
 5. The nonvolatile memorydevice of claim 1, wherein the device comprises a monolithic, threedimensional array of nonvolatile memory cells.
 6. The nonvolatile memorydevice of claim 1, wherein each nonvolatile memory cell comprises a onetime programmable or a rewritable cell selected from at least one ofantifuse, fuse, diode and antifuse arranged in a series, polysiliconmemory effect cell, metal oxide memory, switchable complex metal oxide,carbon nanotube memory, graphene switchable resistance material, phasechange material memory, conductive bridge element, or switchable polymermemory.
 7. The nonvolatile memory device of claim 5, wherein: themonolithic, three dimensional array of nonvolatile memory cells islocated over a silicon substrate; at least one memory cell in a firstdevice level of the array is located over another memory cell in asecond device level over the silicon substrate; and an integratedcircuit comprising a driver circuit for the array of nonvolatile memorycells is located in the silicon substrate or on a surface of the siliconsubstrate.
 8. The nonvolatile memory device of claim 1, furthercomprising a plurality of word lines connected to the plurality ofnonvolatile memory cells; and a plurality of bit lines connected to theplurality of nonvolatile memory cells.
 9. The nonvolatile memory deviceof claim 8, wherein the first direction is a direction along which bitlines of the plurality of nonvolatile memory cells extend.
 10. Thenonvolatile memory device of claim 8, wherein the first direction is adirection along which word lines of the plurality of nonvolatile memorycells extend.
 11. The nonvolatile memory device of claim 8, wherein theplurality of word lines cross the plurality of bit lines at an angle ofabout 60 degrees.
 12. A nonvolatile memory device, comprising: amonolithic, three dimensional array of nonvolatile memory cells locatedover a silicon substrate and comprising a plurality of nonvolatilememory cells arranged in a substantially hexagonal pattern; and anintegrated circuit comprising a driver circuit for the array ofnonvolatile memory cells located in the silicon substrate or on asurface of the silicon substrate, and wherein the nonvolatile memorycells are arranged in a plurality of subarrays which are substantiallyparallelogram shaped and have a non-square corner; wherein each subarrayamong the plurality of subarrays includes a plurality of nonvolatilememory cells arranged in a substantially hexagonal pattern; wherein eachof the plurality of subarrays has parallel sides that extend along afirst direction and a non-parallel side that adjoins a respective drivercircuit block for driving the subarray; wherein the driver circuitblocks for the plurality of subarrays have a staggered layout such thata layout of each driver circuit block is shifted along the firstdirection from a horizontal line that is perpendicular to the firstdirection and passes through the non-square corner by a respectivelateral offset distance; and the lateral offset distances differ amongone another among an entire set of driver circuit blocks that drive theplurality of subarrays.
 13. The nonvolatile memory device of claim 8,wherein: the plurality of nonvolatile memory cells comprises a pluralityof pillar shaped current steering elements; and the substantiallyhexagonal pattern comprises a repeating pattern of seven nonvolatilememory cells having a central nonvolatile memory cell surrounded by sixother nonvolatile memory cells arranged in a hexagonal layout around thecentral nonvolatile memory cell.
 14. The nonvolatile memory device ofclaim 8, wherein the device comprises: a first nonvolatile memory cell,a second nonvolatile memory cell, and a third nonvolatile memory cell;wherein the first nonvolatile memory cell, the second nonvolatile memorycell, and the third nonvolatile memory cell are equidistant from eachother and are located in a same plane.
 15. The nonvolatile memory deviceof claim 14, wherein the first nonvolatile memory cell, the secondnonvolatile memory cell, and the third nonvolatile memory cell have acell half pitch of less than about 32 nm.
 16. The nonvolatile memorydevice of claim 12, wherein each nonvolatile memory cell comprises a onetime programmable or a rewritable cell selected from at least one ofantifuse, fuse, diode and antifuse arranged in a series, polysiliconmemory effect cell, metal oxide memory, switchable complex metal oxide,carbon nanotube memory, graphene switchable resistance material, phasechange material memory, conductive bridge element, or switchable polymermemory.
 17. The nonvolatile memory device of claim 12, furthercomprising: a plurality of word lines connected to the plurality ofnonvolatile memory cells; and a plurality of bit lines connected to theplurality of nonvolatile memory cells.
 18. The nonvolatile memory deviceof claim 17, wherein the first direction is a direction along which bitlines of the plurality of nonvolatile memory cells extend.
 19. Thenonvolatile memory device of claim 17, wherein the first direction is adirection along which word lines of the plurality of nonvolatile memorycells extend.
 20. The nonvolatile memory device of claim 12, furthercomprising: a plurality of word lines connected to the plurality ofnonvolatile memory cells; and a plurality of bit lines connected to theplurality of nonvolatile memory cells; wherein the plurality of wordlines cross the plurality of bit lines at an angle of about 60 degrees.